1. Field of the Invention
This invention generally relates to a memory architecture and a memory writing method for the same, and more particularly to a memory architecture of display device and a memory writing method for the same.
2. Description of the Related Art
FIG. 1 is a schematic circuit of a conventional memory module 100 for portable display devices such as mobile phones or personal digital assistants (PDA). The memory module 100 comprises a memory cell array 102 having a plurality of memory cells 102a arranged as n cell rows and m cell columns, and a pre-charge circuit 104 consisting of several transistors 106. Each memory cell 102a is used for storing one bit, e.g. a low logic level “0” or a high logic level “1”, and generally accomplished by 4T (four MOS transistors) or 6T (six MOS transistors) structure of SRAM cell. A plurality of wordlines WL0, WL1, WL2 and WLn are respectively connected to each cell row in the memory cell array 102. A plurality of pairs of complementary bitlines B0, BB0 and Bm, BBm are respectively connected to each cell column in the memory cell array 102, wherein each bitline B0, BB0, Bm, BBm respectively has a parasitic capacitor CB0, CBB0, CBm, CBBm connected to a common voltage VCOM. The pre-charge circuit 104 has a plurality of outputs 104a respectively connected to each bitline B0, BB0, Bm, BBm.
Before the memory cell array 102 is activated to perform a data writing operation, the input voltage level PRECH of the pre-charge circuit 104 is presented as low logic level such that each transistor 106 is turned on; meanwhile, each parasitic capacitor CB0, CBB0, CBm, CBBm at the bitlines B0, BB0, Bm, BBm is precharged to a voltage level VDD through each output 104a of the pre-charge circuit 104. Then, the input voltage level PRECH is presented as high logic level so as to turn off the pre-charge circuit 104; meanwhile, one of the wordlines WL0, WL1, WL2 and WLn (e.g. wordline WL0) turns on one cell row such that one memory cell 102a (e.g. the leftmost cell memory 102a) in the turned-on cell row can be written by data (logic level “0” or “1”) through the pair of complementary bitlines (e.g. the complementary bitlines B0, BB0) connected thereof.
During the data writing operation, although only one memory cell 102a (e.g. the leftmost cell memory 102a) in the turned-on cell row can be written by data (logic level “0” or “1”), the other memory cells 102a in the same cell row will have their data and complementary data stored thereof applied to their corresponding pairs of complementary bitlines, such that one bitline of each corresponding pair has its parasitic capacitor discharged to a low voltage level (e.g. ground level) from the voltage level VDD. Therefore, before the next data writing operation, the pre-charge circuit 104 charges again each parasitic capacitor CB0, CBB0, CBm, CBBm at the bitlines B0, BB0, Bm, BBm, that is, charges the parasitic capacitors having the low voltage level (e.g. ground level) to the voltage level VDD so as to begin the next data writing operation.
However, in the memory module 100, only one memory cell 102a is written by data during each data writing operation. Further, before each memory cell 102a is to be written by data, the parasitic capacitors having the low voltage level (e.g. ground level) are required to be precharged to the voltage level VDD. Therefore, when the number of memory cells 102a to be written by data increases, the number of times for charging and discharging the parasitic capacitors will relatively increase, which may cause additional power consumption.
Accordingly, the present invention provides a memory architecture of display device and a memory writing method for the same so as to solve the above-mentioned problem existing in the art.